2026-2027 Sem I

Course Information

  • Prerequisites: ACOL1000
  • Credits: 3-0-2
  • Lectures: M4 Classroom 6. M, T, Th 8-9am. M, W 2-3:30pm
  • Labs: M3 Computer Labs 3. W 5-7pm,
  • IRA: Satyam Jay (anz238224 AT iitdabudhabi.ac.ae)
  • Reading material:
  • Practice verilog:

Grading criteria

  • Theory quizzes: 20%. Best (n-1) out of n
  • Lab quizzes: 20%. Best (n-1) out of n
  • Minor exam: 30%
  • Major exam: 30%

Policies

  • Ethics: Please re-read IITD honour code. Academic dishonesty will earn you an F grade and will get a referral to the disciplinary committee. Why should I not cheat?
  • Attendance: Attendance must be over 75%.
  • There will be no makeup quizzes. We will count best (n-1) marks from n quizzes. All quizzes will be pre-announced, i.e., no surprise quizzes. We will take at least 4 theory quizzes and at least 3 lab quizzes.
  • Discussions should be done on Blackboard. Please do not send individual mails.

Tentative topics

  • Digital Systems and Binary Numbers
  • Boolean Algebra and Logic Gates
  • Gate-level Minimization
  • Combinational Logic
  • Synchronous Sequential Logic
  • Registers and Counters
  • Memory and Programmable Logic

We will also learn the Verilog Hardware Description Language and program the Basys3 board.

Disclaimer: Actual course contents may differ.

Schedule

*: Lecture will be longer than 1 hour.

Week Mon Tue Wed Wed Thu
1
2
24 Aug
LEC 1: Introduction
Digital systems. Math basics
25 Aug
LEC 2: Introduction
Transistors. Circuits with n-channel transistors
26 Aug
No lab
28 Aug
LEC 3: Binary numbers
CMOS. Binary, octal, hexadecimal, binary arithmetic
3
31 Aug
LEC 4: Binary numbers
Decimal to binary, ASCII, parity bits, representing long bit strings
01 Sep
LEC 5: Binary numbers
unsigned int, endianness, signed magnitude system, 2's complement
02 Sep
Lab 1: Introduction to Verilog/Vivado
AND/OR gate
04 Sep
LEC 6: Binary numbers
floats. Reference: Section 1, 2
4
07 Sep
LEC 7: Binary numbers
Floats and rounding errors. Quiz 1
09 Sep
LEC 8: Boolean algebra
Huntington postulates, theorems, duality, truth tables, boolean functions, equivalence with schematics with gates
09 Sep
Lab 2: Seven segment display
5
14 Sep
LEC 9: Gate minimization
Canonical and standard forms, two and three variable K-maps
16 Sep
LEC 10: Gate minimization
Four variable K-maps, essential prime implicants, don't care conditions
16 Sep
Lab 3: Mock Lab Exam
6
21 Sep
LEC 11: Gate minimization
Quine-McCluskey method, BDD, other gates
23 Sep
LEC 12: Other logic gates
Nand, Nor, and-or-invert, or-and-invert
23 Sep
Lab Exam 1
7
28 Sep
LEC 13: Other logic gates
Parity with XOR gates. Introduction to combinational circuits
30 Sep
LEC 14: Combinational circuit
Reusing circuit elements
30 Sep
Lab 4: Review Lab Exam 1
8
05 Oct
LEC 15: Combinational circuit
Binary Adder
07 Oct
Class postponed to next Thursday
07 Oct
Lab 5: BCD adder
9
12 Oct
LEC 17: Combinational circuit
Subtractor, multiplier, comparator
14 Oct
LEC 18: Combinational circuit
Decoder, encoder, multiplexer
14 Oct
Lab 6: ALU
16 Oct
Quiz 2 and 3
10
19 Oct
break
21 Oct
break
21 Oct
break
11
26 Oct
mid-semester exam
28 Oct
mid-semester exam
28 Oct
mid-semester exam
12
02 Nov
LEC 19:
04 Nov
LEC 20:
04 Nov
Lab:
13
09 Nov
LEC 21:
11 Nov
LEC 22:
11 Nov
Lab:
14
16 Nov
LEC 23:
18 Nov
LEC 24:
18 Nov
Lab:
15
23 Nov
LEC 25:
25 Nov
LEC 26:
25 Nov
Lab:
16
30 Nov
Commemoration Day
02 Dec
LEC 27:
02 Dec
Lab:
17
07 Dec
LEC 28:
09 Dec
LEC 29:
09 Dec
Lab:
18
14 Dec
LEC 30:
16 Dec
LEC 31:
16 Dec
Lab: